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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843004-02 is a 4 output LVPECL Synthesizer optimized to generate clock HiPerClockSTM frequencies for a variety of high performance applications and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. This device can select its input reference clock from either a crystal input or a single-ended clock signal and can be configured to generate a number of different output frequencies via the 3 frequency select pins (F_SEL2:0). The ICS843004-02 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter. This ensures that it will easily meet clocking requirements for high-speed communication protocols such as 10 and 12 Gigabit Ethernet, 10 Gigbit Fibre Channel, and SONET. This device is also suitable for next generation serial I/O technologies like serial ATA and SCSI and is conveniently packaged in a small 24-pin TSSOP package.
FEATURES
* Four 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Crystal input range: 14MHz - 37.78MHz * VCO Range: 560MHz - 680MHz * Supports the following applications: SONET, Ethernet, Serial ATA, SCSI and HDTV * RMS phase jitter @ 155.52MHz (12kHz - 20MHz): 0.91ps (typical) Offset Noise Power 100Hz ............... -97.1 dBc/Hz 1kHz .............. -121.6 dBc/Hz 10kHz .............. -124.9 dBc/Hz 100kHz .............. -125.1 dBc/Hz * Full 3.3V supply mode * 0C to 70C ambient operating temperature
ICS
FUNCTION TABLE
Inputs F_SEL2 0 0 0 0 1 1 1 1 F_SEL1 F_SEL0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M Divider Value 18 24 24 32 32 32 32 40 N Divider Value 3 4 8 1 2 4 8 8
PIN ASSIGNMENT
nQ1 Q1 VCCo Q0 nQ0 MR nPLL_SEL nc nc VCCA F_SEL0 VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VCCO Q3 nQ3 F_SEL2 nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT F_SEL1
BLOCK DIAGRAM
nPLL_SEL Pulldown
N /1 /2 /3 /4 (default) /8
ICS843004-02
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body Q0 G Package Top View nQ0
Q1 nQ1
XTAL_IN
OSC
XTAL_OUT TEST_CLK
Pulldown
0
0
1
Phase Detector
VCO
1
nXTAL_SEL Pulldown
Q2
M /18 /24 /32 (default) /40
nQ2 Q3 nQ3
MR Pulldown 3 F_SEL0:2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 22 4, 5 6 Name nQ1, Q1 VCCO Q0, nQ0 MR Type Output Power Ouput Input Description Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pullup Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Negative supply pin. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
7 8, 9 10 11, 19 12 13 14, 15 16 17 18 20, 21 23, 24
nPLL_SEL nc VCCA F_SEL0, F_SEL2 VCC F_SEL1 XTAL_OUT, XTAL_IN VEE TEST_CLK nXTAL_SEL nQ3, Q3 Q2, nQ2
Input Unused Power Input Power Input Input Power Input Input Output Output
NOTE: Pulldown and Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3. OUTPUT CONFIGURATION
Inputs F_SEL2 0 1 1 1 1 0 1 0 0 0 1 0 F_SEL1 F_SEL0 1 1 1 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 1 1 0
AND
FREQUENCY RANGE FUNCTION TABLE
M Divider Value 24 40 40 32 32 32 32 24 24 24 32 18 N Divider Value 8 8 8 4 8 1 2 4 8 4 4 3 VCO (MHz) 594 593.4066 640 622.08 622.08 622.08 622.08 600 600 637.5 625 562.5 Output Frequency (MHz) 74.25 74.1758245 80 155.52 77.76 622.08 311.04 150 75 159.375 156.25 187.5 Application HDTV HDTV SCSI SONET SONET SONET SONET SATA SATA 10 Gig Fibre Channel 10 Gig Ethernet 12 Gig Ethernet
Reference Clock 24.75 14.8351649 16 19.44 19.44 19.44 19.44 25 25 26.5625 19.53125 31.25
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 125 12 Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage nPLL_SEL, nXTAL_SEL, Input F_SEL0:F_SEL2, MR Low Voltage TEST_CLK Input High Current TEST_CLK, MR, F_SEL1 nPLL_SEL, nXTAL_SEL F_SEL0, F_SEL2 IIL Input Low Current TEST_CLK, MR, F_SEL1 nPLL_SEL, nXTAL_SEL, F_SEL0, F_SEL2 Test Conditions Minimum Typical 2 -0.3 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5 Maximum VCC + 0.3 0.8 1.3 15 0 5 Units V V V A A A A
IIH
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pf parallel resonant crystal. 14 Test Conditions Minimum Typical Maximum 37.78 50 7 Units MHz MHz pF Fundamental
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fOUT f VCO Parameter Output Frequency PLL VCO Lock Range Output Skew; NOTE 1 RMS Phase Jitter; NOTE 2, 3 PLL Lock Time Output Rise/Fall Time 20% to 80% 155.52MHz, 12kHz -20MHz F_SEL0:F_SEL2 = 0 Test Conditions Minimum 74.17 562.5 562.5 15 0.91 TBD 450 Typical Maximum 637.5 640 580 Units MHz MHz MHz ps ps ms ps %
tsk(o) tjit(O)
tL tR / tF
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: Phase jitter is dependent on the input source used. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
V CC , VCCA, VCCO
Qx
SCOPE
nQx Qx nQy
LVPECL
nQx
Qy
VEE
tsk(o)
-1.3V0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
OUTPUT SKEW
Noise Power
Phase Noise Mask
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQ0:nQ3 Q0:Q3
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843004-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: INPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS843004-02 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL2 C2 33p X1 18pF Parallel Crystal XTAL1 C1 27p
ICS843004-02
Figure 2. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
Figure 4 shows an example of ICS843004-02 application schematic. In this example, the device is operated at VCC=3.3V. The decoupling capacitor should be located as close as possible to the power pin. Both input options are shown. The device can either be driven using a quartz crystal or a 3.3V
LVCMOS signal. For the LVPECL output drivers, only two termination examples are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note.
MR nPLL_SEL VCC VCCA R2 10 3.3V C3 10uF C4 0.01u R3 133 VCCO F_SEL0 Zo = 50 Ohm + R5 133
Logic Control Input Examples
VDD
VCC Zo = 50 Ohm 12 11 10 9 8 7 6 5 4 3 2 1
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
-
VCC F_SEL0 VCCA NC NC nPLL_SEL MR nQ0 Q0 VCCO Q1 nQ1
U4 843004-02
R4 82.5
R6 82.5
RD1 Not Install
RD2 1K
F_SEL1 XTAL_OUT XTAL_IN VEE TEST_CLK nXTAL_SEL F_SEL2 nQ3 Q3 VCCO Q2 nQ2
To Logic Input pins
To Logic Input pins
VCC=3.3V VCCO=3.3V
(U1-3)
VCC
(U1-12)
(U1-22)
F_SEL1
13 14 15 16 17 18 19 20 21 22 23 24
Zo = 50 Ohm C1 0.1uF C2 0.1uF C3 0.1uF Zo = 50 Ohm C2 33pF VCC Q1 Ro ~ 7 Ohm R8 43 Driv er_LVCMOS nXTAL_SEL F_SEL2 Zo = 50 Ohm X1 19.44MHz 18pF C1 27pF VCCO R5 50 R6 50 +
Optional Y-Termination
R7 50
FIGURE 4. ICS843004-02 SCHEMATIC EXAMPLE
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
0 1
65C/W
2.5
62C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
TRANSISTOR COUNT
The transistor count for ICS843004-02 is: 3467
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX
FOR
24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
843004AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843004AG-02 ICS843004AG-02T Marking ICS843004A02 ICS843004A02 Package 24 Lead TSSOP 24 Lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature 0C to 70C 0C to 70C
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843004AG-02
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